Segmentation of memory is utilized in some processors to organize the virtual address space into a logical structure that resembles the user's view of memory. Segment sizes can conform to the size of logical procedures and modules utilized in block structured languages such as Pascal and C. Accordingly, segments differ from pages because they are not of fixed length.
A logical address comprises a portion specifying a segment number and an effective address portion specifying an offset into the segment. The segment number is utilized to access a segment descriptor in a segment table. The segment descriptor includes the real base address of the segment and a limit value defining the size of the segment.
In microprocessors such as the Intel 80386 the program instructions are stored in a control segment of memory and a fetch of an instruction from outside the control segment, i.e., a segmentation violation, could cause a serious program malfunction. Accordingly, the addresses of fetched instructions must be checked to determine whether the addresses are included in the control space.
In the 80386 the translation from a logical address to a physical address is done by a Segmentation Unit. While it translates, the Segmentation Unit checks for segmentation violations.
One method of checking for segmentation violations is to use a comparator for processing in parallel the number of bits necessary to determine whether the offset specified by the effective address is greater than the limit number in the descriptor. If the limit number is 2.sup.n then the comparator must compare two n-bit numbers to check for segmentation violations.
A substantial saving in the amount of logic required in the segmentation unit results if a smaller comparator can be utilized for limit checking.